(China (Mainland))
Product Summary
The K7B803625B-PC65 is a 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. The K7B803625B-PC65 is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous.
Parametrics
K7B803625B-PC65 absolute maximum ratings: (1)Voltage on VDD Supply Relative to VSS, VDD: -0.3 to 4.6 V; (2)Voltage on VDDQ Supply Relative to VSS, VDDQ: VDD V; (3)Voltage on Input Pin Relative to VSS, VIN: -0.3 to VDD+0.3 V; (4)Voltage on I/O Pin Relative to VSS, VIO: -0.3 to VDDQ+0.3 V; (5)Power Dissipation, PD: 1.6 W; (6)Storage Temperature, TSTG: -65 to 150℃; (7)Operating Temperature, Commercial, TOPR: 0 to 70℃; Industrial, TOPR: -40 to 85℃; (8)Storage Temperature Range Under Bias, TBIAS: -10 to 85℃.
Features
K7B803625B-PC65 features: (1)Synchronous Operation; (2)2 Stage Pipelined operation with 4 Burst; (3)On-Chip Address Counter; (4)Self-Timed Write Cycle; (5)On-Chip Address and Control Registers; (6)3.3V+0.165V/-0.165V Power Supply; (7)I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O; (8)5V Tolerant Inputs Except I/O Pins; (9)Byte Writable Function; (10)Global Write Enable Controls a full bus-width write; (11)Power Down State via ZZ Signal; (12)LBO Pin allows a choice of either a interleaved burst or a linear burst; (13)Three Chip Enables for simple depth expansion with No Data Contention only for TQFP; 2cycle Enable, 1cycle Disable; (14)Asynchronous Output Enable Control; (15)ADSP, ADSC, ADV Burst Control Pins; (16)TTL-Level Three-State Output; (17)100-TQFP-1420A; (18)Operating in commeical and industrial temperature range.
Diagrams
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K7B801825B |
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K7B801825M |
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